Method of electroplating copper over a patterned dielectric layer

ABSTRACT

In a new method of electroplating metal onto a patterned dielectric layer including small diameter vias and large diameter trenches, a pulse reverse electroplating sequence with a two-component chemistry is modified to substantially fill the vias, while in a subsequent DC deposition the bulk material is deposited to completely fill the large diameter trenches. Thus, good control quality compared to conventional three-component chemistry electroplating is obtained while the superior characteristics of a metal layer deposited by a two-component chemistry are preserved. The method is particularly advantageous in electroplating copper.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention generally relates to the fabrication ofintegrated circuits, and, more particularly, to the formation ofmetallization layers, wherein a metal is deposited over a patterneddielectric layer and excess metal is subsequently removed by chemicalmechanical polishing (CMP).

[0003] 2. Description of the Related Art

[0004] In every new generation of integrated circuits, device featuresare further reduced, whereas the complexity of the circuits steadilyincreases. Reduced feature sizes not only require sophisticatedphotolithography methods and advanced etch techniques to appropriatelypattern the circuit elements, but also places an ever-increasing demandon deposition techniques. Presently, the minimum feature sizes approach0.1 μm, which allows the fabrication of fast-switching transistorelements covering only a minimum of chip area. However, as a consequenceof the reduced feature sizes, the available floor space for the requiredmetal interconnects decreases, while the number of necessaryinterconnections between the individual circuit elements increases. Adecreasing cross-sectional area of metal connects makes it necessary toreplace the commonly used aluminum by a metal that allows a highercurrent density at a reduced electrical resistivity to obtain reliablechip interconnects with high quality. In this respect, copper has provento be a promising candidate due to its advantages such as lowresistivity, high reliability, high heat conductivity, relatively lowcost and a crystalline structure that may be controlled to obtainrelatively large grain sizes. Furthermore, copper shows a significantlyhigher resistance against electromigration and therefore allows highercurrent densities while the resistivity is low, thus allowing theintroduction of lower supply voltages.

[0005] Despite the many advantages of copper compared to aluminum,semiconductor manufacturers in the past have been reluctant to introducecopper into the manufacturing sequence for several reasons. One majorissue in processing copper in a semiconductor line is the copper'scapability of readily diffusing in silicon and silicon dioxide atmoderate temperatures. Copper diffused into silicon may lead to asignificant increase in the leakage current of transistor elements,since copper acts as a deep-level trap in the silicon band-gap.Moreover, copper diffused into silicon dioxide may compromise theinsulating properties of silicon dioxide and may lead to higher leakagecurrents between adjacent metal lines, or may even form shorts betweenneighboring metal lines. Thus, great care must be taken to avoid anycontamination of silicon wafers with copper during the entire processsequence.

[0006] A further issue arises from the fact that copper may not beeffectively applied in greater amounts by deposition methods, such asphysical vapor deposition (PVD) and chemical vapor deposition (CVD),which are well-known and well-established techniques in depositing othermaterials, such as aluminum. Accordingly, copper is now commonly appliedby a wet process, such as electroplating, which provides, compared toelectroless plating, the advantages of a higher deposition rate and aless complex electrolyte bath. Although at a first glance electroplatingseems to be a relatively simple and well-established deposition method,the demand of reliably filling high aspect ratio openings withdimensions of 0.1 μm, as well as wide trenches having a lateralextension on the order of micrometers, renders electroplating of copper,as well as other metals that may be used in metallization layers, ahighly complex deposition method, in particular as subsequent processsteps, such as chemical mechanical polishing and any metrologyprocesses, directly depend on the quality of the electroplating process.

[0007] With reference to FIGS. 1a-1 f, a typical process sequence formanufacturing a metallization layer will now be described. According toFIG. 1a, a semiconductor device 100 comprises a substrate 101 includingcircuit elements, such as transistors, resistors, capacitors, and thelike, which, for the sake of simplicity, are not depicted in FIG. 1a. Afirst dielectric layer 102 is formed above the substrate 101 and isseparated by an etch stop layer 103 from a second dielectric layer 104.For example, the first and second dielectric layers 102, 104 may becomprised of silicon dioxide, whereas the etch stop layer 103 maycomprise silicon nitride. In the second dielectric layer 104, an opening105 is formed having the dimensions of a via to be formed subsequentlyin the first dielectric layer 102. The methods for forming thesemiconductor device 100 as depicted in FIG. 1a are well-established inthe art and a description thereof will be omitted.

[0008]FIG. 1b schematically shows the semiconductor device 100 with thevia 105 formed in the first dielectric layer 102 and an overlying trench106 formed in the second dielectric layer 104. Moreover, a wide trench107 is formed in the second dielectric layer 104 that has asignificantly larger lateral dimension than the via 105 and the trench106. The inner surfaces of the via 105, the trench 106 and the widetrench 107 are covered by a barrier diffusion layer 108 followed by acopper seed layer 109.

[0009] The via 105, the trench 106 and the wide trench 107 are formed byanisotropic etching, wherein the etch process stops at the etch stoplayer 103, which has been removed at the via 105 in a preceding,separate etch step. Commonly, the barrier diffusion layer 108, such astantalum nitride or titanium nitride, is formed by chemical vapordeposition followed by a sputter deposition process to form the seedlayer 109 that acts as a current distribution layer for the subsequentelectroplating process.

[0010]FIG. 1c depicts the semiconductor device 100 with a copper layer110 filled in the via 105, the trench 106 and the wide trench 107,wherein the copper layer 110 exhibits an extra thickness so as tocompletely fill the wide trench 107 over which the topology of thecopper layer 110 is significantly determined by the underlying widetrench 107.

[0011] After depositing the copper layer 110, an anneal step may beperformed to establish a required crystallinity in the copper layer 110.Thereafter, the semiconductor device 100 is subjected to a CMP processto remove the excess copper and to provide for a planar surface thatallows the formation of a further metallization layer. Since CMP is initself a highly complex process, the result of the polishing processstrongly depends on the properties of the copper layer 110. For example,a minor non-uniformity of the copper layer 110 at different positions onthe wafer may already lead to an intolerable variation in the resultingcopper lines, since, while in a region with an increased copperthickness the excess metal is still being removed and thus theunderlying trenches are still intact, in a region with a reduced copperthickness, the underlying copper trench, for example trench 106, mayalready be exposed and subjected to undesired polishing, resulting in aloss of copper within the trench, which may compromise its reliability.Hence, any non-uniformities obtained by the copper plating procedure mayplace a great burden on the CMP process, thereby jeopardizing thequality of the metal lines.

[0012]FIG. 1d schematically shows the semiconductor structure 100 aftercompletion of the CMP process, wherein the excess copper, as well asportions of the diffusion barrier layer 108 at the exposed surface areasof the second dielectric layer 104, are removed. Thus, metal lines 106and 107 are obtained that are electrically insulated from each other.Usually, a further dielectric diffusion barrier layer is deposited onthe semiconductor substrate 100 after completion of the metallizationsequence so as to passivate the exposed copper surface of the metallines 106 and 107 and avoid out-diffusion of copper into overlyingdielectrics and metals.

[0013] For reliable metal interconnects, it is not only important todeposit the copper as uniformly as possible over the entire surface of a200 or even 300 mm diameter substrate, but it is also important toreliably fill vias having an aspect ratio of approximately 10:1 withoutany voids or defects. As a consequence, it is essential to deposit thecopper in a highly non-conformal manner, as will be explained withreference to FIGS. 1e and 1 f, which schematically show the via 105 inenlarged form.

[0014] In FIG. 1e, filling in of the via 105 is depicted in an initialstate, wherein copper has accumulated with a certain thickness athorizontal portions 111, i.e., at the bottom of the trench 106 (see FIG.1d), whereby the thickness at a corner 112 shows a maximum copperaccumulation. At the bottom corners 113, the copper amount is minimal,whereas in the center of the via bottom 114, an increased amount ofcopper is accumulated; however, in a significantly less amount than onthe horizontal portion 111 and the corner 112. The copper distributionin FIG. 1e corresponds to a “normal” copper electroplating deposition inwhich a DC current is supplied to the electrolyte bath containing anacidic copper-containing solution. The discrepancy in the copperdistribution is mainly caused by the varying density of copper ions atthe various regions, since, in regions of sub-micron dimensions, thenumber of available copper ions is substantially determined by diffusionrather than by electrolyte flow. As the number of copper ions per unitarea is substantially the same, the number of ions arriving at the topside of the via 105 have to be distributed over the entire (large) innersurface, thereby leading to a significantly reduced deposition ratecompared to the horizontal portion 111. Moreover, at an initial state,the deposition rate may also depend on the electrical resistance of theunderlying barrier diffusion layer and copper seed layer 108, 109, sothat any non-uniformity of these layers also translates into anon-uniformity of the bulk copper layer 110. Typically, sputterdepositing of the copper seed layer into the high-aspect ratio via 105may result in a layer thickness profile that is quite similar to theprofile of the initial copper layer as shown in FIG. 1e and thusenhances the undesired deposition behavior. The right-hand side of FIG.1e shows a void 115 that may be formed during an electroplating processdue to the increased copper accumulation at the corners 112. Since thevoid 115 significantly reduces the current capability of the via 105, acorresponding circuit element may show a decreased reliability or may beprone to premature failure due to the increased current density in theremaining copper of the via 105.

[0015] Accordingly, great efforts have been made to establish anelectroplating technique that allows a highly non-conformal depositionof a metal, such as copper, in which the via 105 is filled substantiallyfrom bottom to top.

[0016]FIG. 1f schematically shows an initial state of a desired copperfill-in method in which the via 105 is substantially filled from thebottom also with an enhanced deposition rate at the sidewalls 116 of thevia 105. Contrary to the “normal” deposition, the deposition rate at thehorizontal portions 111 and the corners 112 is significantly reduced, sothat finally a completely-filled via covered by a substantially uniform“excess” layer 110 is formed, as shown on the right-hand side of FIG.1f.

[0017] It has been recognized that a fill-in behavior as described inFIG. 1f may be obtained by controlling the deposition kinetics withinthe via 105 and on the horizontal portions and edges 111 and 112. Thismay be achieved by introducing additives into the electrolyte bath toinfluence the rate of copper ions that deposit on the respectivelocations. For example, an organic agent of relatively large,slow-diffusing molecules, such as polyethylene glycol, may be added tothe electrolyte and preferentially absorbed on the flat surface andcorner portions 111 and 112. Hence, contact of copper ions at theseregions is reduced and thus the deposition rate is decreased. Acorrespondingly-acting agent is also often referred to as a“suppressor.” On the other hand, a further additive, including smallerand faster-diffusion molecules, may be used that preferentially absorbswithin the via 105 and enhances the deposition rate by offsetting theeffects of the suppressor additive. A corresponding additive is oftenalso referred to as an “accelerator.” In addition to using anaccelerator and a suppressor, it has been found that a simple DCdeposition, i.e., deposition by supplying a substantially constant DCcurrent, may not result in the required deposition behavior despite theemployment of accelerator and suppressor additives. Instead, theso-called pulse reverse deposition has become a preferred operation modein depositing copper. In the pulse reverse deposition technique, currentpulses of alternating polarity are applied to the electrolyte bath so asto deposit copper on the substrate during forward current pulses and torelease a certain amount of copper during reverse current pulses,thereby improving the fill capability of the electroplating process.Typically, the current and/or the duration of the forward current pulsesis equal or higher than that of the reverse pulses to achieve a netdeposition effect.

[0018]FIG. 2a qualitatively shows a current time diagram for carryingout a copper deposition with an electrolyte bath including a suppressorand an accelerator additive, which allows one to substantiallycompletely fill the vias 105 and trenches 106 as well as the widetrenches 107 depicted in FIG. 1. Although the quality of the copperdeposited into the vias and trenches in view of the number of defectsand voids is strongly affected by the composition of the electrolytebath and thus requires a thorough control of the additives containedtherein, the provision of an accelerator and a suppressor is nowwell-established and well-controllable so that a long-term stability ofsuch a two-component chemistry electrolyte bath may be readily ensured.

[0019] The electroplating recipe including an electrolyte bath with asuppressor and an accelerator with a pulse reverse operation mode,although allowing the reliable filling of high-aspect ratio vias,exhibits one major drawback in view of filling wide trenches 107.

[0020]FIG. 2b schematically shows a typical result of electroplatingcopper with the above-explained recipe, wherein prominent protrusions120 are formed at the edges of the wide trench 107. The formation of theprotrusions 120 may be avoided if a large amount of “overdeposition” iscarried out, wherein, however, the surface roughness of the copper layer110 significantly increases and wherein, most importantly, thesubsequent CMP process has to remove a large amount of excess metal,thereby increasing process time and thus the amount of copper erosionformed during the CMP process.

[0021] Thus, it has become standard practice to modify the electrolytebath by adding a further agent, a so-called leveler, in an extremelyminute dose to slow down the copper deposition rate at the edges of thewide trench 107. When using such a three-component chemistry in theelectrolyte bath, i.e., an electrolyte bath including a suppressor, anaccelerator and a leveler, to obtain the required deposition behavior,it is essential to reliably control the low concentration of the levelerwithin tightly-set tolerances to provide for stable electroplatingconditions. Measuring a low concentration of a leveler in a concentratedsuppressor and accelerator environment is, however, quite complex andrequires great effort in terms of time and equipment.

[0022] In view of the above-mentioned problems, it would therefore behighly desirable to provide an electroplating process that minimizes theburden on the subsequent CMP process while allowing simple control ofthe electrolyte conditions.

SUMMARY OF THE INVENTION

[0023] Generally, the present invention is directed to a method thatprovides an electroplating sequence with a two-component chemistry inthe electrolyte bath, wherein the requirements for different products(i.e., different layouts), different technologies (i.e., differentminimal feature sizes), and different metal layers (i.e., varying sizeand density of metal lines) may readily be fulfilled while at the sametime the burden on post-electroplating processes is relaxed. To thisend, the present invention proposes to use an additional DCelectroplating step after the pulse reverse fill-in step of small viasand trenches is substantially completed.

[0024] According to one illustrative embodiment of the presentinvention, a method of electroplating a metal on a substrate including adielectric layer having a small-diameter and a large diameter openingcomprises providing a two-component electrolyte bath including asuppressor and an accelerator and positioning the substrate in theelectrolyte bath. Next, a pulse reverse sequence is performed tosubstantially fill the small-diameter opening. Subsequently, a DCdeposition is carried out to completely fill the large diameter of theopening.

[0025] According to a further illustrative embodiment of the presentinvention, a method of depositing a metal over a substrate including apatterned dielectric layer with a small diameter opening and a largediameter opening by electroplating comprises providing an electrolytebath including a suppressor additive and an accelerator additive andpositioning the substrate in the electrolyte bath. The method furtherincludes generating a plurality of forward current pulses, each with afirst time period, and a plurality of reverse current pulses, each witha second time period, in the electrolyte bath to deposit metal on thesubstrate during the forward current pulses, wherein the forward currentpulses and the reverse current pulses are provided in an alternatingfashion. Additionally, a DC current is generated for a predefined thirdtime period in the electrolyte bath to deposit metal on the substrate,wherein the first and second time periods are less than the third timeperiod.

BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The invention may be understood by reference to the followingdescription taken in conjunction with the accompanying drawings, inwhich like reference numerals identify like elements, and in which:

[0027]FIGS. 1a-1 f schematically show cross-sectional views of asemiconductor device during various manufacturing stages when receivinga copper metallization layer;

[0028]FIG. 2a schematically shows a diagram depicting current vs. timein a typical pulse reverse electroplating process;

[0029]FIG. 2b schematically shows the result of electroplating copperover a wide trench using a two-component chemistry and the conventionalpulse reverse recipe;

[0030]FIG. 3 schematically depicts an idealized electroplating reactorin an oversimplified manner;

[0031]FIG. 4a schematically depicts a diagram illustrating a currentwaveform vs. time according to one illustrative embodiment of thepresent invention; and

[0032]FIG. 4b schematically shows the result of one illustrativeembodiment of the two-component chemistry in connection with adeposition current waveform as shown in FIG. 3a.

[0033] While the invention is susceptible to various modifications andalternative forms, specific embodiments thereof have been shown by wayof example in the drawings and are herein described in detail. It shouldbe understood, however, that the description herein of specificembodiments is not intended to limit the invention to the particularforms disclosed, but on the contrary, the intention is to cover allmodifications, equivalents, and alternatives falling within the spiritand scope of the invention as defined by the appended claims.

DETAILED DESCRIPTION OF THE INVENTION

[0034] Illustrative embodiments of the invention are described below. Inthe interest of clarity, not all features of an actual implementationare described in this specification. It will of course be appreciatedthat in the development of any such actual embodiment, numerousimplementation-specific decisions must be made to achieve thedevelopers' specific goals, such as compliance with system-related andbusiness-related constraints, which will vary from one implementation toanother. Moreover, it will be appreciated that such a development effortmight be complex and time-consuming, but would nevertheless be a routineundertaking for those of ordinary skill in the art having the benefit ofthis disclosure.

[0035] The present invention is based on the inventor's finding that thesuperior characteristics of a two-component chemistry electrolyte bath,in terms of controllability and surface quality of the final metallayer, compared to a three-component chemistry may be maintained, whileat the same time a reliable and substantially conformal filling of widetrenches, having a lateral extension on the order of magnitude of one toseveral micrometers, is ensured in that a final DC step is carried outto deposit a “cap” layer required for completely filling the widetrenches. Due to the relatively simple composition of the electrolytebath, reproducible electroplating conditions may be maintained duringthe processing of a large number of substrates. Moreover, by varying theduration and/or the amount of current applied during the DC cap layerdeposition, the ratio of the thickness of the cap layer, i.e., theportion of the metal deposited during the final DC deposition step, tothe total layer thickness may readily be adjusted, allowing theadaptation of the process recipe to different metals, different layoutsof the metallization layers, to different minimal feature sizes and to avarying density of metal lines on different metallization layers.

[0036] With reference to FIGS. 3 and 4, illustrative embodiments of thepresent invention will now be described, wherein for the sake ofsimplicity, it is also partially referred to FIG. 1, and to the samereference numerals are used for corresponding parts in FIGS. 3 and 4 andthe detailed description of those corresponding parts is omitted.

[0037] Moreover, in the following illustrative embodiments, copper isreferred to as the metal to be deposited by electroplating since copper,as previously noted, is expected to be mainly used in futuresophisticated integrated circuits, and the embodiments describedhereinafter are particularly advantageous in electroplating copper. Thepresent invention is, however, also applicable to other metals and metalcompounds and metal alloys.

[0038]FIG. 3 shows a schematic and oversimplified view of anelectroplating reactor 300 which may be used to describe the presentinvention. In general, the result of an electroplating process dependson the kinetics within the electroplating reactor. However, the basicconcept of the present invention may be applied to any type ofelectroplating reactor presently used in the fabrication of integratedcircuits, including copper metallization layer. Thus, it should be bornein mind that the electroplating reactor 300, in reality, comprisesadditional means for obtaining the desired electrolyte flow within thereactor, such as shields, supply lines, means for rotating the waferand/or shields, and the like. In one embodiment, an electroplatingreactor may be used that is available from Semitool Inc. under the nameLT210C™. It should be noted that the present invention may be applied toany electroplating reactor.

[0039] The reactor 300 additionally comprises an electrode 301 coupledto a power source 302, which in the present invention is adapted toprovide an output current with a predefined magnitude, duration andpolarity. Opposite to the electrode 301, a substrate 100 is positioned,such as the semiconductor device 100 of FIG. 1, including the patterneddielectric layers 102 and 104 with the barrier diffusion layer 108 andthe copper seed layer 109. The reactor 300 further comprises anelectrolyte 303, the main component of which is a copper sulfateacidified with sulfuric acid. The electrolyte 303 further comprises asuppressor additive 304 and an accelerator additive 305, a concentrationof which may readily be controlled, for example by polarizationmeasurements on a copper layer deposited on a previously processed testor product substrate. The copper layer includes a certain minute amountof the suppressor 304 and the accelerator 305 that modifies the opticalcharacteristics of the copper layer when reflecting an incident lightbeam. Such two-component electrolyte baths are readily available, forexample from Shiply under the name of Nanoplate. The accelerator may becomprised of propane sulfonic acid. A typical concentration of theaccelerator is in the range of approximately 1-10 ml/l. The suppressormay be comprised of a polyalkylene glycol type polymer. A typicalconcentration of the suppressor is in the range of approximately 1-30ml/l. It should be noted that the present invention is not restricted toa specific electrolyte and may be practiced with any electrolytescurrently available or electrolytes that will be available in thefuture.

[0040] Upon application of voltage pulses of alternating polarityincluding a first polarity, i.e., a polarity that makes the electrode301 the anode, and the substrate 100 the cathode, a current is induced,leading to a migration of the copper ions to the surface of thesubstrate 100. Thereby, the voltage pulse of the first polarity isselected such that a substantially constant current of a predefinedheight is generated, which will be referred to as forward current pulse.The corresponding migration of copper ions is indicated by arrows 306.Each voltage pulse of the first polarity is followed by a voltage pulseof a second polarity, i.e., of a polarity that makes the electrode 301the cathode and the substrate 100 the anode, which is applied andadjusted so as to generate a substantially constant current with apredefined height (in the reverse direction) as indicated by arrows 307.The current generated by the voltage of the second polarity will bereferred to as reverse current pulse. As previously noted, thealternating application of forward current pulses and reverse currentpulses leads to a reliable deposition of copper within small diameteropenings such as the via 105 and the trench 106 in the dielectric layers104 and 102.

[0041] The height of the forward current pulses and the reverse currentpulses depends on the size of the substrate 100 and the structure of thepatterned dielectric layer 104 and 102. Typically, a current ofapproximately 1 to 20 ampere for a substrate surface including vias andtrenches down to 0.1 μm and below is selected for the forward currentpulses. The corresponding reverse pulses may range from approximately1-20 ampere. Typically, a duration T₁ of a single forward current pulsemay range from approximately 1-100 seconds. The duration T₂ of a singlereverse current pulse may be in the range of approximately 1-100seconds. During the application of alternating forward pulses and thereverse pulses for a predefined time period T_(S), herein also referredto as pulse reverse sequence, small diameter openings, i.e., vias 105and possibly the overlying trenches 106 are substantially filled,whereas the substantially conformal deposition over the wide trench 107requires an additional deposition step to reliably completely fill thewide trench 107. Contrary to the conventional process recipe, in whichthe pulse height, the duration (T₁, T₂) of the individual pulses and thetime period T_(S) are selected so as to obtain the requiredover-deposition, resulting, in the present example of a two-componentchemistry, in additional protrusions 120, as shown in FIG. 2, in thepresent invention the over-deposition is accomplished by a final DCcurrent deposition step, whereby the height of the current and/or theduration of the DC current is selected to obtain the required amount ofover-deposition to reliably fill the trench 107.

[0042]FIG. 4a qualitatively depicts the time dependency of the currentsapplied to the substrate 100. During the pulse reverse sequence, copperis deposited on the substrate 100 in the forward pulses of duration T₁corresponding to T₁ and the magnitude of the current. During the reversecurrent pulses, a certain degree of redistribution of the copper takesplace depending on the period T₂ and the magnitude of the (reverse)current. After the pulse reverse sequence T_(S), the DC step is carriedout for a time period T₃ with a predefined height of the DC current. Itshould be noted that, in principle, the current time integral of thevarious current pulses is a measure of the amount of copper deposited onthe substrate 100. Thus, in some embodiments requiring a highthroughput, the magnitude of the current during the DC step may beraised to obtain a desired high overall deposition rate, therebyslightly compromising the surface quality of the copper layer 110.Moreover, by appropriately selecting T_(S) and/or T₃ or the ratio ofT_(S) to T₃, i.e., by selecting the ratio of the “via fill-in”capability to the (DC) “conformal deposition” capability, the finalsurface quality of the copper layer, and thus the “burden” for thesubsequent CMP, may be adjusted.

[0043]FIG. 4b schematically shows the structure 100 after applying aprocess sequence as shown in FIG. 4a, wherein the copper layer 110 isdeposited over the wide trench 107 with a thickness that ensurescomplete filling of the wide trench 107 after the subsequent CMPprocess. Moreover, any protrusions, such as those shown in FIG. 2b, mayreliably be avoided, thus generating a high quality copper layer 110without the need of providing a highly complex three-componentelectrolyte bath including a leveler.

[0044] After deposition of the copper, the structure 100 may be annealedto adjust the final grain size of the copper layer 110, whichsignificantly affects the characteristics of the completed copper lineswith respect to electromigration.

[0045] The quality of the surface of the copper layer 110 may beestimated on the basis of the amount of light reflected from an incidentlight beam, since a rougher surface will scatter a larger portion of theincident light beam and thus reduce the intensity of the reflected lightbeam. A plurality of semiconductor substrates 100 with a copper layer110 formed according to a typical standard two-component plating recipeand a plurality of semiconductor substrates 100 having a copper layerformed according to the embodiments as described above have beenexamined and revealed that the reflectivity of the substrates processedaccording to the standard process recipe exhibit a reflectivity ofapproximately 3%, whereas the substrates processed according to thepresent invention exhibit a reflectivity of approximately 32%. Thus, thesignificant improvement in reflectivity according to the presentinvention not only indicates a smoother surface of the copper layer 110but also allows one to more reliably obtain optical measurement resultsfrom correspondingly processed substrates. For example, the CMP processis commonly monitored optically to detect the end of the polishingprocess, wherein a light beam is directed to the surface while beingpolished and the intensity of the reflected light beam is detected.Consequently, an increased initial reflectivity provides for less noisyand thus more reliable endpoint signals. In particular, the endpointdetection signal of the substrates processed according to the presentinvention, exhibits a substantially flat plateau with a sharp fallingedge that indicates the end of the process more precisely, whereas thesubstrates processed according to the standard reverse pulse recipeexhibit a varying plateau with a noisy signal at the falling edge of theendpoint detection signal. Thus, the endpoint of the CMP process will bedetermined more precisely by applying the process recipe according tothe present invention. Moreover, as already indicated by the highreflectivity of the copper layer 110, the CMP process of the copperlayer 110 is less critical and also requires significantly less polishtime. Examinations performed on the above prepared substrates revealed apolish time reduction of approximately 23%. The reduction of polish timealso significantly contributes to an improvement in copper surfacequality due to reduced formation of copper erosion and discoloration. Afurther advantageous effect of the present invention regards dishing anderosion occurring during the chemical mechanical polishing of the copperlayer 110. Dishing of copper trenches, i.e., the faster removal ofcopper compared to the neighboring dielectric, and erosion, i.e.,removal of dielectric material, compared to the initial layer thickness,is also relaxed due to the reduced polish time, the improved detectionof the endpoint and the high surface quality of the deposited copper.Moreover, the defect level is remarkably reduced.

[0046] Thus, the present invention allows an improved process andcontrollability compared to standard three-component chemistry withoutcompromising the superior characteristics of reverse pulseelectroplating using a two-component chemistry, such as improvedresistance against electromigration of the completed copper lines due toan increased grain size of the copper, reliable filling of smalldiameter openings, such as vias in the range of 0.1 μm, and of largediameter openings, such as wide trenches on the order of severalmicrometers.

[0047] The particular embodiments disclosed above are illustrative only,as the invention may be modified and practiced in different butequivalent manners apparent to those skilled in the art having thebenefit of the teachings herein. For example, the process steps setforth above may be performed in a different order. Furthermore, nolimitations are intended to the details of construction or design hereinshown, other than as described in the claims below. It is thereforeevident that the particular embodiments disclosed above may be alteredor modified and all such variations are considered within the scope andspirit of the invention. Accordingly, the protection sought herein is asset forth in the claims below.

What is claimed:
 1. A method of depositing a metal over a substrate including a patterned dielectric layer with a small diameter opening and a large diameter opening by electroplating, the method comprising: providing an electrolyte bath including a suppressor additive and an accelerator additive; positioning the substrate in said electrolyte bath; generating a plurality of forward current pulses, each with a first time period, and a plurality of reverse current pulses, each with a second time period, in said electrolyte bath to deposit metal on said substrate, wherein said forward current pulses and said reverse current pulses are provided in an alternating fashion; and generating a DC current for a predefined third time period in said electrolyte bath to deposit metal on said substrate, wherein the first and second time periods are less than the third time period.
 2. The method of claim 1, wherein at least one of a height of the forward current pulse, a height of the reverse current pulse, the first time period, the second time period and a time interval for applying the current pulses and the reverse current pulses is selected to completely fill at least the small diameter opening.
 3. The method of claim 1, wherein at least one of a height of the DC current and the third time period is controlled to adjust the final thickness of the metal layer deposited on and in the patterned dielectric layer.
 4. The method of claim 1, wherein said forward current pulses and said reverse current pulses are applied for a predefined time interval and a ratio of said time interval and said third time period is controlled to adjust a quality of said metal layer.
 5. The method of claim 1, further comprising annealing said substrate to adjust a grain size in said metal layer.
 6. The method of claim 1, wherein said electrolyte bath includes copper ions.
 7. A method of electroplating a metal over a substrate including a surface portion with a patterned dielectric layer including a small diameter opening and a large diameter opening, the method comprising: providing an electrolyte bath including a two-component additive chemistry for non-conformal filling in said small diameter opening; positioning the substrate in the electrolyte bath; performing a pulse reverse plating sequence to substantially fill the small diameter opening; and applying a DC current of a predefined height for a predefined time period to completely fill the large diameter opening.
 8. The method of claim 7, wherein a time period of the pulse reverse plating sequence is controlled to adjust a surface quality of the final metal layer.
 9. The method of claim 7, wherein at least one of said predefined height and said predefined time period of the DC current is selected to adjust a surface quality of the final metal layer.
 10. The method of claim 7, wherein a height and a duration of forward current pulses and reverse current pulses in said pulse reverse plating sequence is selected to substantially completely fill the small diameter opening.
 11. The method of claim 7, wherein at least one of a height and a duration of forward current pulses and reverse current pulses in said pulse reverse plating sequence, a time period of said pulse reverse plating sequence, the predefined height of said DC current, and the predefined time period of the DC current is controlled to adjust a surface quality of the final metal layer.
 12. The method of claim 7, wherein said metal comprises copper.
 13. The method of claim 7, further comprising annealing said substrate to adjust a grain size in said metal layer. 